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at1367a/b/c/d preliminary product information 1mhz, 800ma synchronous buck converter with power good detector & ldo 7f, no.9, park avenue ii, science-based industri al park, hsinchu 300,taiwan, r. o.c. tel: 886-3-563-0878 fax: 886-3-563-0879 www: http://www.aimtron.com.tw 3/2/2006 rev:1.2 email: service@aimtron.com.tw 1 features ? operation voltage 2.5v~6.0v ? oscillation frequency 1mhz ? output current maximum 800ma dc-dc converter ? built-in 400ma/ldo ? power good indicator with time delay adjustable ? built-in current limit ? built-in uvlo ? built-in thermal shutdown ? built-in ldo on/off control metal option applications ? power supply for slim type devices general description the at1367a/b/c/d provides complete control for a dc/dc converter optimized for hight-performance microprocessor applications. it consists of a synchronous step-down dc/dc converter and a high-speed ldo regulator connected in series with the dc/dc converter output. a power good detector and ldo on/off control is also built-in(metal option). dc/dc converter is operated on current mode architecture for excellent line and load transient response. 1mhz operation frequency is allowing the use of small surface mount induct or and capacitor. the internal synchronous switch increases efficiency and eliminates the need for an external schottky diode. the at1367a/b/c/d is a family of low-noise synchronous step-down dc/dc converters that is ideally suited for systems powered form a 1-cell li-ion battery or from a 3-cell to 4-cell nicd, nimh, or alkaline battery. it can also be used to usb-based power system. block diagram current sense osc + slope r s q sw vref + - /pg vcc pgnd shoot throught pg delay out2 out1 + - vref current limit 5 uvlo vreg vref - + vref r2 r1 uvlo *out2=2.5v/1.8v metal option ctl control ldo ctl ctl auto discharge vcc 0.9 x vref r4 r3 *ctl and /pg metal option 0.35ua r5 vbg vbg agnd + - aimtron reserves the right without notice to change this circuitry and specifications.
at1367a/b/c/d preliminary product information 1mhz, 800ma synchronous buck converter with power good detector & ldo 7f, no.9, park avenue ii, science-based industri al park, hsinchu 300,taiwan, r. o.c. tel: 886-3-563-0878 fax: 886-3-563-0879 www: http://www.aimtron.com.tw 3/2/2006 rev:1.2 email: service@aimtron.com.tw 2 pin assignment 1 2 3 4 5 6 7 8 at1367 9 10 at1367a at1367b AT1367C at1367d /pg /pg ctl ctl ldo 2.5v ldo 1.8v ldo 2.5v ldo 1.8v dfn10 (top view) ordering information a:1367an b:1367bn c:1367cn d:1367dn date code * for more marking information, contact our sales representative directly. pin description symbol pin no. descript pg 1 power good indicator output(ative hi) /pg or ctl 2 /power good output (ative lo) or ldo on/off control ( metal option ) vcc 3 power supply sw 4 out1 inductor node pgnd 5 power ground vbg 6 reference output voltage agnd 7 analog ground delay 8 the capacitor connection terminal for a reset delay time setup out1 9 ldo intput and dc/dc output out2 10 ldo output part number package marking 1367 n dfn10,green
at1367a/b/c/d preliminary product information 1mhz, 800ma synchronous buck converter with power good detector & ldo 7f, no.9, park avenue ii, science-based industri al park, hsinchu 300,taiwan, r. o.c. tel: 886-3-563-0878 fax: 886-3-563-0879 www: http://www.aimtron.com.tw 3/2/2006 rev:1.2 email: service@aimtron.com.tw 3 absolute maximum ratings * 1 rated value parameter symbol min. max. unit power supply voltage vcc -0.3 +6.5 v ctl , out1, out2 -0.3 vcc v input pin voltage sw, pg, /pg -0.3 vcc+0.3 v p-channel switch source current (dc) ? - 1 a n-channel switch sink current (dc) ? - 1 a peak sw sink and source current ? - 1.5 a thermal resistance from junction to ambient ja dfn10 - 35.25 0 c/w thermal resistance from junction to case jc dfn10 - 3 0 c/w operating temperature t a ? -35 +85 0 c storage temperature ? -55 +150 0 c hbm - 2 kv esd susceptibility*2 mm - 200 v 1. stresses beyond those listed under ?absolute maxi mum ratings? may cause permanent damage to the device. these are stress ratings only , and functional operation of th e device at these or any other conditions beyond those indicated in th e operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . 2. device are esd sensitive. handling precaution recommended. the human body model is a 100pf capacitor discharged through a 1.5k ? resistor into each pin. recommended operating conditions (ta=+25 0 c) values parameter symbol min. typ. max. unit power supply voltage v in 2.5 -- 6.0 operating temperature* t op -20 +25 +85 c operating junction temperature t j - - +150 c * using x5r or x7r input capacitors.
at1367a/b/c/d preliminary product information 1mhz, 800ma synchronous buck converter with power good detector & ldo 7f, no.9, park avenue ii, science-based industri al park, hsinchu 300,taiwan, r. o.c. tel: 886-3-563-0878 fax: 886-3-563-0879 www: http://www.aimtron.com.tw 3/2/2006 rev:1.2 email: service@aimtron.com.tw 4 electrical characteristics (vcc = 3.6v,t a =+25 , unless otherwise noted. ) values parameter symbol condition min. typ. max. unit dc/dc converter vcc uvlo v uv vcc=3v 2v sweep - 2.4 - v uvlo hysteresis width v uvhy - 100 - mv input supply range v cc 2.5 - 6.0 v quiescent current i s active mode - 500 - a output1 voltage accuracy v out1 -2 - +2 % output1 voltage line-regulation v out1-line vcc=3.5v to 6.0v - 0.1 0.5 % output1 variation with temperature t a =-20 to +85 - 0.5 1.0 % feedback current i out1 v out1 =3.3v - 6 - ua current limit i cl1 vin=5v, v out1 =3.3v 1.10 1.25 1.50 a maximum output current i o vin=5v, v out1 =3.3v, l=4.7uh - - 800 ma fosc1 vout1=3.3v 0.8 1.0 1.2 mhz oscillator frequency fosc2 vout1=0v - 200 -- khz r ds(on) of p-channel mosfet r pfet i lx = 600ma - 0.3 0.4 ? r ds(on) of n-channel mosfet r nfet i lx = -600ma - 0.25 0.35 ? sw leakage current i swl - 0.1 1 a control block ctl threshold v ctl v ctl =0v~2v sweep metal option 0.3 1.0 1.5 v ctl leakage current i ctl v ctl =5.0v metal option - 6 - a pg on voltage v pgon i pg =1ma - - 0.4 v pg hysteresis width v pgthys - 80 - mv pg pin leak current i pgtlk v /pg =5.0v - - 1 ua /pg on voltage v /pgon i /pg =1ma metal option - - 0.4 v /pg hysteresis width v /pgthys metal option - 80 - mv /pg pin leak current i /pgtlk v /pg =5.0v metal option - - 1 ua delay pin charge current i delay 0.3 0.5 0.8 ua ldo output2 voltage accuracy v out2 -2 - +2 % current limit i cl2 v out1 =3.3v 450 - - ma dropout voltage v dv i out2 =400ma - 400 600 mv load regulation ? v out2 i out2 =1ma 100ma - 15 50 mv line regulation lr i out2 =100ma, v out1 =3.5v 6.0v - 0.05 0.25 % ripple rejection rate psrr i out2 =100ma, f=1khz - 60 - db out2 leakage current i out2lk ctl=0v, v out2 =2.5v/1.8v metal option - 6 - ua
at1367a/b/c/d preliminary product information 1mhz, 800ma synchronous buck converter with power good detector & ldo 7f, no.9, park avenue ii, science-based industri al park, hsinchu 300,taiwan, r. o.c. tel: 886-3-563-0878 fax: 886-3-563-0879 www: http://www.aimtron.com.tw 3/2/2006 rev:1.2 email: service@aimtron.com.tw 5 typical characteristics efficiency vs. output1 current 50 55 60 65 70 75 80 85 90 95 100 10 100 1000 output1 current(ma) efficiency(%) l=2.2uh l=3.3uh l=4.7uh ch1 vin, ch2 vout1, ch3 pg, ch4 /pg ch1 vo u t 1 , c h 2 vo u t 2 , c h 4 iout1 iout1=100ma~400ma, iout2=300ma efficiency vs. output1 current 50 55 60 65 70 75 80 85 90 95 100 10 100 1000 output1 current(ma) efficiency(%) vcc=5v vcc=4.2v vcc=3.6v ch1 vout1, ch2 vout2, ch3 pg, ch4 ctl ch1 vo u t 1 , c h 2 vo u t 2 , c h 4 iout2 iout1=300ma, iout2=100ma~300ma
at1367a/b/c/d preliminary product information 1mhz, 800ma synchronous buck converter with power good detector & ldo 7f, no.9, park avenue ii, science-based industri al park, hsinchu 300,taiwan, r. o.c. tel: 886-3-563-0878 fax: 886-3-563-0879 www: http://www.aimtron.com.tw 3/2/2006 rev:1.2 email: service@aimtron.com.tw 6 typical application circuits sw /pg vcc pgnd pg delay out2 out1 to dsp to dsp vin 5.0v vout1 3.3v/300ma vout2 2.5v/400ma 10uf 4.7uh 10uf at1367a 27nf 2.2uf vbg 10nf agnd 100k 100k figure 1 sw /pg vcc pgnd pg delay out2 out1 vin 5.0v vout1 3.3v/300ma vout2 1.8v/400ma 10uf 4.7uh 10uf at1367b 27nf 2.2uf vbg 10nf agnd to dsp to dsp 100k 100k figure 2
at1367a/b/c/d preliminary product information 1mhz, 800ma synchronous buck converter with power good detector & ldo 7f, no.9, park avenue ii, science-based industri al park, hsinchu 300,taiwan, r. o.c. tel: 886-3-563-0878 fax: 886-3-563-0879 www: http://www.aimtron.com.tw 3/2/2006 rev:1.2 email: service@aimtron.com.tw 7 typical application circuits ( continued ) sw vcc pgnd pg delay out2 out1 ctl to dsp vin 5.0v vout1 3.3v/400ma vout2 2.5v/400ma 10uf 4.7uh 10uf 100k AT1367C from dsp 2.2uf 27nf vbg agnd 10nf figure 3 sw vcc pgnd pg delay out2 out1 ctl to dsp vin 5.0v vout1 3.3v/400ma vout2 1.8v/400ma 10uf 4.7uh 10uf 100k at1367d from dsp 2.2uf 27nf vbg agnd 10nf figure 4
at1367a/b/c/d preliminary product information 1mhz, 800ma synchronous buck converter with power good detector & ldo 7f, no.9, park avenue ii, science-based industri al park, hsinchu 300,taiwan, r. o.c. tel: 886-3-563-0878 fax: 886-3-563-0879 www: http://www.aimtron.com.tw 3/2/2006 rev:1.2 email: service@aimtron.com.tw 8 typical application circuits ( continued ) sw /pg vcc pgnd pg delay out2 out1 vin 5.0v vout1 3.3v/300ma vout2 1.8v/400ma 10uf 4.7uh 10uf 100k at1367b 27nf 2.2uf vbg 10nf agnd to dsp to dsp from /pg 100k 100k 1m 0.1uf figure 5 application information capacitor selection in continuous mode, the source current of the top mosfet is square wave of duty cycle. the primary function of the input cap acitor is to provide a low impedance loop for the edges of pulsed current drawn by the at1367a/b/c/d. a load step at the output can induce ringing at the input vin. this ringing can couple to the output and be mistaken as loop instability. the oscillation can be improved by add the capacitance of the input capac itor. a typical value is 10 f ceramic (x5r or x7r), poscap or aluminum polymer. these capacitors will provide good high frequency bypassing and their low esr will reduce resistive losses for higher efficiency. the input capacitor rms current varies with th e input voltage and th e output voltage. the equation for the maximum rms current in the input capacitor is: ) 1 ( in o in o omax rms v v v v i i ? =
at1367a/b/c/d preliminary product information 1mhz, 800ma synchronous buck converter with power good detector & ldo 7f, no.9, park avenue ii, science-based industri al park, hsinchu 300,taiwan, r. o.c. tel: 886-3-563-0878 fax: 886-3-563-0879 www: http://www.aimtron.com.tw 3/2/2006 rev:1.2 email: service@aimtron.com.tw 9 the output capacitor depends on the suit able ripple voltage. low ripple voltage corresponds to lower effective series resist ance (esr). the output ripple voltage is determined by: the output capacitor rms ri pple current is given by: vbg capacitor a vbg pin is provided to decouple the bandgap reference voltage. an external capacitor connected form vb g to gnd reduces noise pr esent on th e internal reference voltage, which in turn significan tly reduces output noise and also improves psrr. larger capacitor values may be used to further improve psrr, but result in a longer time period (slower turn on) to settle output voltage when power is initially applied. ldo for general purposes, use a 2.2uf capacito r on the ldo output. larger capacitor values and lower esr provide better supply noise rejection and tr ansient response. a higher value input capacitor may be necessary if large, fast transients are anticipated . ceramic capacitors have the lowest esr, and will offer the best ac performance. when choosing the input and output ceramic capacitors, choose the x5r or x7r dielectric formulations. these dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. inductor selection the inductor is chosen based on the desire d ripple current. large value inductors lower ripple current and small value inducto rs result in higher ripple current. always consider the losses associat ed with the dcr and its effect on the total converter ) 8 1 ( out l out fc esr i v + ? ? ? in out in out rms v f l v v v i ? = ) ( 3 2 1
at1367a/b/c/d preliminary product information 1mhz, 800ma synchronous buck converter with power good detector & ldo 7f, no.9, park avenue ii, science-based industri al park, hsinchu 300,taiwan, r. o.c. tel: 886-3-563-0878 fax: 886-3-563-0879 www: http://www.aimtron.com.tw 3/2/2006 rev:1.2 email: service@aimtron.com.tw 10 efficiency when selecting an inductor. th e inductor is selected to limit the ripple current to some predetermined value, typica lly 20~40% of the full load current at the maximum input voltage. the formula of inductance value is as below: ) ( 4 . 0 ~ 2 . 0 max out l i i = ? ? ? ? ? ? ? ? ? ? ? = in out l out v v i f v l 1 l t v v i i i i on out in o l o pk ? + = ? + = 2 ) ( 2 power good indicator with adjustable time delay the pg and /pg pin terminal is an open dr ain output of n-mos. connect a resistor from pg and /pg pin to vcc or out1 to create a logic signal. if out1 pin is less than 2.97v (typ.) this pin is pulled to ground. when out1 pin is above 2.97v and with a delay time this pin is open. pg and /pg pin is forced low when in uvlo. the formula of adjustable delay time is as below : delay i c time delay 8 . 0 = ? the dissipation the power loss is given by: in s s f r out in n on ds out p on ds out dc dc loss v i f t t i v d r i d r i p + + + ? + = ? ? ? ) ( ) 1 ( 1 ) ( 2 1 ) ( 2 1 ) ( ) ( 2 1 2 ) ( out out out ldo loss v v i p ? = ) ( ) ( ) ( ) ( ldo loss dc dc loss ja a max j p p t t + + = ?
at1367a/b/c/d preliminary product information 1mhz, 800ma synchronous buck converter with power good detector & ldo 7f, no.9, park avenue ii, science-based industri al park, hsinchu 300,taiwan, r. o.c. tel: 886-3-563-0878 fax: 886-3-563-0879 www: http://www.aimtron.com.tw 3/2/2006 rev:1.2 email: service@aimtron.com.tw 11 inductors surface mount inductance( h) manufacturer/part no. manufacturer website 3.3 sumida cdrh4d28-3r3 4.7 sumida cdrh5d18-4r7 www.sumida.com 3.3 mitsumi c3-k1.8l-3r3 mitsumi c4-k1.8l-3r3 www.mitsumi.co.jp 3.3 abc sh40283r3ysb 4.7 abc sh40284r7ysb www.atec-group.com capacitors surface mount capacitance( f) manufacturer/part no. manufacturer website 22 tdk c3216x5r0j 226m www.tdk.com 47 tdk c3225x5r0j46m www.tdk.com 10 grm42-6x5r 106k6.3 www.murata.com 2.2 taiyo lmk212bj225 md www.t-yuden.com 4.7 taiyo jmk212bj475 mg www.t-yuden.com
at1367a/b/c/d preliminary product information 1mhz, 800ma synchronous buck converter with power good detector & ldo 7f, no.9, park avenue ii, science-based industri al park, hsinchu 300,taiwan, r. o.c. tel: 886-3-563-0878 fax: 886-3-563-0879 www: http://www.aimtron.com.tw 3/2/2006 rev:1.2 email: service@aimtron.com.tw 12 pc board layout 1. the most critical aspect of the layout is the placement of the input capacitor c2. it must be placed as close as possible to the at1367a/b/c/d to reduce the input ripple voltage. 2. power loops on the input and output of the converter should be laid out with the shortest and widest traces possible. the longer and na rrower the trace, the higher resistance and inductance it will have. the length of traces in series with the capacitors increases its esr and esl and reduces their effectiveness at high frequency. 3. the out1 pin should connect to c1 direc tly. and the route should be away from the noise source, such as inductor of sw line. 4. grounding all components at the same point may effectively reduce the occurrence of loop.
at1367a/b/c/d preliminary product information 1mhz, 800ma synchronous buck converter with power good detector & ldo 7f, no.9, park avenue ii, science-based industri al park, hsinchu 300,taiwan, r. o.c. tel: 886-3-563-0878 fax: 886-3-563-0879 www: http://www.aimtron.com.tw 3/2/2006 rev:1.2 email: service@aimtron.com.tw 13 package outline : dfn10
at1367a/b/c/d preliminary product information 1mhz, 800ma synchronous buck converter with power good detector & ldo 7f, no.9, park avenue ii, science-based industri al park, hsinchu 300,taiwan, r. o.c. tel: 886-3-563-0878 fax: 886-3-563-0879 www: http://www.aimtron.com.tw 3/2/2006 rev:1.2 email: service@aimtron.com.tw 14 reflow condition (ir/convection or vpr reflow ) classification reflow profiles profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (t l to t p ) 3 c/second max. 3 c/second max. preheat -temperature min(tsmin) -temperature max (tsmax) -time (min to max)(ts) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: -temperature (t l ) -time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak/classification temperature(t p ) see table 1 see table 2 time within 5 c of actual peak temperature (t p ) 10-30 seconds 10 seconds max. ramp-down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. * all temperatures refer to topside of the package, measured on the package body surface. classification reflow profiles(cont.) table 1. snpb entectic process C package peak reflow temperatures package thickness volume mm 3 <350 volume mm 3 350 <2.5mm 240+0/-5 225+0/-5 2.5mm 225+0/-5 225+0/-5 table 2. pb - free process C package classification reflow temperatures package thickness volume mm 3 <350 volume mm 3 350-2000 volume mm 3 >2000 <1.6mm 260+0 260+0 260+0 1.6mm - 2.5mm 260+0 250+0 245+0 2.5mm 250+0 245+0 245+0 *tolerance: the device manufacturer/supplier sha ll assure process compatibility up to and including the stated classifi cation temperature (this means peak reflow temperature +0 ? . for example 260 ? +0 ? ) at the rated msl level.

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